The subject application is related to subject matter disclosed in Japanese Patent Application No. 2000-285983 filed on Sep. 20, 2000 in Japan to which the subject application claims priority under Paris Convention and which is incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory integrated circuit, and more particularly to a semiconductor memory such as a DRAM for conducting parallel/serial conversion of read/write data by using a shift register to read/write data at a high speed.
2. Related Background Art
Conventionally, there is known a DRAM which controls data transfer between internal main data lines provided in a cell array region and I/O terminals whose number is smaller than that of the internal main data lines by using a shift register to realize a high-speed cycle. The shift register has a function for converting parallel read data from the cell array into serial data in synchronization with a clock and transmitting the converted data to an I/O circuit, and converting serial write data from the I/O terminals into parallel data and transferring the converted data to the data lines.
In this type of DRAM, the present applicant has first proposed a technique for optimizing arrangement of the cell array, the shift register, the peripheral I/O circuit and others in order to assure the symmetric property of data propagation in a chip and realize the margin of the considerable read/write operation (U.S. Pat. No. 6,198,649).
In the basic structure, four memory cores are symmetrically arranged to a rectangular chip in the vertical (y direction) and horizontal (x direction) directions. Here, the memory core is a cell array range which can be independently activated and includes a cell array including a bit line sense amplifier, a row decoder for selecting a word line and a column decoder for selecting a bit line. The data lines of each memory core are pulled out between the memory cores which are opposed to each other in the vertical direction. The shift register for controlling transfer of read/write data is arranged together with the data line sense amplifier circuit between the memory cores opposed to each other in the vertical direction. The peripheral circuit is arranged between the memory cores opposed to each other in the vertical direction and the memory cores opposed to each other in the horizontal direction.
In case of a 256-bit DRAM, each memory core includes 64 Mbits. Each memory core is divided into the cell arrays each having 32 Mbits in the horizontal direction, and the row decoder is arranged between these cell arrays. Each 64-Mbit memory core has 64 main data lines. With a column address designated by one column cycle, 16 column selection lines are simultaneously activated in this 64-Mbit memory core, and 4-bit data for one column line, i.e., a total of 64-bit parallel read/write data is allocated to 64 main data lines.
In case of producing such conventional DRAMs in large quantities, test cost is an important problem. In order to reduce the test cost, a larger number of memories which can be simultaneously tested by a memory tester is preferable. As one major factor for determining the number of memories which can be simultaneously measured by this memory tester, there is a redundancy algorithm for a capacity of a fail address memory (FAM) for storing a defective address in a memory tester and for failure remedy when the DRAM adopts the redundant circuit system.
Explaining this question in briefly, it is assumed that a capacity of the FAM of the memory tester is m bits, the test of a memory chip having a capacity of n bits. Since an area in the FAM corresponding to n bits is used in order to store an address of a defective cell, the number of the memory chips which can be simultaneously measured is m/n.
On the other hand, it is assumed that a unit of redundancy replacement is two word lines with respect to the row system and the number of bit lines which can be simultaneously selected by one column selection line is 4 as a unit with respect to the column system. Here, one bit of the row address of a defective address can be compressed and two bits of the column address of the same can be compressed respectively, and a total of 3 bits can be compressed and then stored in the FAM. As a result, the number of memory chips which can be simultaneously measured is 23xc3x97m/n.
However, the above is only the simplified explanation, and a defect in a redundant cell portion must be also considered. Further, the algorithm may completely differ depending on the mode of the redundancy, and the simple data compression can not be necessarily conducted as in the above example.
Furthermore, even if the data compression itself does not have any restriction, most of memory testers have such a limitation as that designation of the data compression can not be changed during the test. This becomes a problem when the memory chip is a parity product in particular.
For example, in case of the regular 256-Mbit DRAM which is not a parity product, I/O terminal numbers can be continuously associated with every eight continuous lines in 64 (the number of wirings is doubled and hence 128 because complementary data lines are actually used) main data lines arranged in one 64-Mbit memory core. Moreover, when a range of every four data lines in each memory core is determined as one segment which can be a range of the defective column replacement, a combination of the I/O terminal numbers associated with the four main data lines in each segment is also uniquely determined. In this case, it is possible to clear the restriction of data compression of the memory tester, i.e., the restriction that only one set of I/O compression can be designated during the test.
On the contrary, in case of a parity production obtained by adding one-bit parity bit to the 256-Mbit DRAM for the eight-bit parallel output, one segment of four main data lines is added, and the memory capacity becomes 288 Mbits. In addition, nine main data lines for parallel output and nine I/O terminals DQ0 to DQ8 are provided.
Here, if the column redundancy is adopted, one segment includes 64 column selection lines and at least one spare column selection line, and activation of one column selection line causes four bit lines to be simultaneously connected to four data lines. If there is a defective column, replacement by the spare column line is carried out in units of one segment.
In case of this type of parity product, the I/O terminal numbers associated with every four main data lines in each segment in the memory core become irregular by the usual data line wiring method. FIG. 9 shows the state of the main data line arrangement.
FIG. 9 shows a half of a 72-Mbit memory core, i.e., 36 main data lines MDQ of the cell array corresponding to 36 Mbits. Reference character DQn less than v greater than added to an I/O terminal number assigned to the main data line MDQ means a v-th serial data of an n-th I/O terminal. That is, the serial data is transmitted in the order of DQn less than 0 greater than , DQn less than 1 greater than , . . . DQn less than 3 greater than .
Table 1 shows assignment of the I/O terminals of the main data lines with respect to the nine segments segment0 to segment8 in this example.
Ignoring each serial data number in  less than  greater than  in Table 1 and paying attention to the I/O terminal number, namely, xe2x80x9cnxe2x80x9d in xe2x80x9cDQnxe2x80x9d, for example, the segment0 and the segment8 commonly use a combination of [DQ0, DQ1, DQ2, DQ3]. However, for example, the segment3, 5 include DQ2 and DQ3 and use a combination different from that of the segment0, 8.
According to the restriction conditions for data compression of the memory tester mentioned above, when taking notice to a given I/O terminal number in Table 1, for example, xe2x80x9cDQ1xe2x80x9d during the test, only one combination of the I/O terminal numbers including this I/O terminal number in each segment is allowed. Therefore, I/O data compression is impossible in combinations shown in Table 2.
The above-described problem can be solved if a capacity of the FAM of the memory tester is large, but additional installation of the FAM leads to increase in the test cost. If the FAM is not additionally provided, the number of memory chips which can be simultaneously measured is restricted, which also results in increase in the test cost.
Another problem concerning the main data line arrangement shown in FIG. 9 is that a change in design is not easy when a non-parity product of 256 Mbits is cut down with the above-described parity product of 288 Mbits as a mother product.
The technique for producing a small-capacity memory having a basic standard similar to that of a large-capacity mother product by cut-down is important because the redesign cost of the memory can be reduced. However, when a part of the I/O terminal number DQ8 corresponding to the parity bit is excluded from the structure of the cell array and the main data line shown in FIG. 9, the structure illustrated in FIG. 10 can be obtained. Shaded portions in FIG. 10 correspond to the parts excluded by cut-down. For layout of the memory, respective halves of the two segment2, 6 are cut of f as shown in the drawing. Considering that repetition of a regular pattern forms one segment, cut-down is not easy.
As described above, in the prior art DRAM, the number of memory chips which can be simultaneously tested is restricted because of the limitation of functions of the memory tester, which leads to increase in the test cost, and the cut-down design is no easy.
A semiconductor memory circuit comprising:
a memory cell array;
a plurality of main data lines configured to conduct reading and writing of plural bits in parallel with respect to said memory cell array; and
a shift register configured to convert parallel data read from said memory cell array to said main data lines into serial data and supplying the converted data to data input/output terminals, and configured to convert write data supplied from said data input/output terminals in series into parallel data and supplying the converted data to said main data lines,
at least portion of a plurality of said main data lines being arranged to be across each other between said memory cell array and said shift register.